Presentation : Formal Methods and VLSI

Simulation will not work in future! That much I am sure of. You just can not simulate all the possible combination described specification in a modern day VLSI design. Even if you have 1000 of computers at your disposal. It would be foolhardy to do so. However, simulation with formal methods may yields wonderful results. We concentrate on the formal methods here. Any improvement in these methods will be of great values for VLSI verification.

See attached beamer presentation.

formal_verification_vlsi_ver0.9

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